Language Breakdown
Lines of code distribution across 9 owned repositories
5.4M
Total LOC
Verilog
5,127,210 lines
94.4%
N/A
Python
137,645 lines
2.5%
N/A
C
76,281 lines
1.4%
N/A
Scala
61,549 lines
1.1%
N/A
Makefile
11,179 lines
0.2%
N/A
Other
14,774 lines
0.3%
N/A
I
I-Shaped Developer
I-shapedSpecialist — deep expertise in Verilog
Verilog
Python
C
Scala
Makefile
Collaboration Network
Global Impact visualization
Repos
44
PRs
0
Growth
+18%
Top Collaborators
No collaborator data yet.
Coding Streak
Contribution activity over the past year
1 day
1,030
Contributions
816
Commits
138
Pull Requests
Jun
Jul
Aug
Sep
Oct
Nov
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Jan
Feb
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Apr
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Followers
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Top Repositories
iob-soc
RISC-V System on Chip Template Based on the picorv32 Processor
1
0
Makefile
fdk-aac
A standalone library of the Fraunhofer FDK AAC code from Android.
0
0
C++
zmk-config
0
0
versat-ai
0
0
C
fusesoc-public
Public library of FuseSoC cores
0
0
Standard ML
iob-uart16550-fs
0
0
Verilog
iob-cache-fs
0
0
Verilog
iob-eth-fs
0
0
Verilog
fusesoc-cores
FuseSoC standard core library
0
0
iob-vexiiriscv
0
0
Verilog
Open Source Impact
Contributions to external projects
615 merged PRs
fusesoc/fusesoc-cores
165
IObundle/iob-soc
163
IObundle/iob-cache
200
IObundle/iob-picorv32
14
IObundle/iob-eth
11
IObundle/iob-spi
0
IObundle/iob-vexriscv
1
IObundle/iob-clint
2
IObundle/iob-uart16550
1
IObundle/iob-plic
1
Contributed to 24 repositories